--- drivers/net/ethernet/realtek/r8169soc.c	2021-07-07 21:45:27.000000000 +0000
+++ drivers/net/ethernet/realtek/r8169soc.c	2020-06-20 10:56:32.145294431 +0000
@@ -901,8 +901,8 @@
 		if (c->check(tp) == high)
 			return true;
 	}
-	netif_info(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
-		  c->msg, !high, n, d);
+//	netif_info(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
+//		  c->msg, !high, n, d);
 	return false;
 }
 
@@ -1170,8 +1170,8 @@
 	 * According to hardware specs a 20us delay is required after read
 	 * complete indication, but before sending next command.
 	 */
-		
-	netif_info(tp, drv, tp->dev, "read phy reg %x value %x!\n", reg, value);
+
+	//netif_info(tp, drv, tp->dev, "read phy reg %x value %x!\n", reg, value);
 
 	udelay(20);
 
--- drivers/rtc/rtc-rtd1295.c	2021-07-07 21:45:27.000000000 +0000
+++ drivers/rtc/rtc-rtd1295.c	2021-11-10 20:57:47.022836339 +0000
@@ -106,20 +106,20 @@
 	spin_lock_irqsave(&rtk_rtc_lock, flags);
 
 	if (!en) {
-		dev_err(dev, "rtk_rtc_disable");
+//		dev_err(dev, "rtk_rtc_disable");
 		writel(0x00, rtk_rtc_base + REG_RTCEN);
 	} else if ( (readl(rtk_rtc_base + REG_RTCEN) & 0xff) != 0x5A ) {
-		dev_warn(dev, "rtk_rtc_enable");
+//		dev_warn(dev, "rtk_rtc_enable");
 		writel(0x5A, rtk_rtc_base + REG_RTCEN);
 	} else
 		dev_warn(dev, "rtk_rtc already enabled ");
-
-	dev_info(dev, "enable REG_SEC = 0x%x \n", readl(rtk_rtc_base + REG_RTCSEC));
-	dev_info(dev, "enable REG_MIN = 0x%x \n", readl(rtk_rtc_base + REG_RTCMIN));
-	dev_info(dev, "enable REG_HR = 0x%x \n", readl(rtk_rtc_base + REG_RTCHR));
-	dev_info(dev, "enable REG_DATA_LOW = 0x%x \n", readl(rtk_rtc_base + REG_RTCDATE_LOW));
-	dev_info(dev, "enable REG_DATE_HIGH = 0x%x \n", readl(rtk_rtc_base + REG_RTCDATE_HIGH));
-
+/*
+ 	dev_info(dev, "enable REG_SEC = 0x%x \n", readl(rtk_rtc_base + REG_RTCSEC));
+ 	dev_info(dev, "enable REG_MIN = 0x%x \n", readl(rtk_rtc_base + REG_RTCMIN));
+ 	dev_info(dev, "enable REG_HR = 0x%x \n", readl(rtk_rtc_base + REG_RTCHR));
+ 	dev_info(dev, "enable REG_DATA_LOW = 0x%x \n", readl(rtk_rtc_base + REG_RTCDATE_LOW));
+ 	dev_info(dev, "enable REG_DATE_HIGH = 0x%x \n", readl(rtk_rtc_base + REG_RTCDATE_HIGH));
+*/
 	spin_unlock_irqrestore(&rtk_rtc_lock, flags);
 }
 
@@ -214,7 +214,7 @@
 	if( enable_virtual_rtc == 1 ) {
 		wd_time_seconds = readl(wd_spi_base);
 		wd_time_xor_seconds = readl(wd_spi_base + 0x4);
-		dev_info(dev,"Read time from flash = [0x%08X, 0x%08X]\n", wd_time_seconds, wd_time_xor_seconds);
+//		dev_info(dev,"Read time from flash = [0x%08X, 0x%08X]\n", wd_time_seconds, wd_time_xor_seconds);
 		if( (wd_time_seconds ^ wd_time_xor_seconds) == UINT_MAX ) {
 			ts->tv_sec = wd_time_seconds;
 			ts->tv_nsec = 0;
@@ -233,7 +233,7 @@
 	hour = readl(rtk_rtc_base + REG_RTCHR);
 	day = readl(rtk_rtc_base + REG_RTCDATE_LOW);
 	day += readl(rtk_rtc_base + REG_RTCDATE_HIGH)<<8;
-	dev_info(dev,"sec=0x%x , min=0x%x . day=0x%x \n", sec, min, day); //hcy test 
+// 	dev_info(dev,"sec=0x%x , min=0x%x . day=0x%x \n", sec, min, day); //hcy test
 
 	if (sec == 0 && !retried) {
 		retried++;
@@ -294,6 +294,7 @@
 
 	rtk_read_persistent_clock(dev, &ts);
 	rtc_time_to_tm(ts.tv_sec, tm);
+/*
 	dev_info(dev,"time read as %04d-%02d-%02d %02d:%02d:%02d",
 								tm->tm_year + 1900,
 								tm->tm_mon + 1,
@@ -301,7 +302,7 @@
 								tm->tm_hour,
 								tm->tm_min,
 								tm->tm_sec);
-
+*/
 	return rtc_valid_tm(tm);
 }
 
@@ -330,11 +331,10 @@
 	// Using 4 bytes to store seconds is enough
 	buf[0] = (unsigned int)cur_sec;
 	buf[1] = (unsigned int)cur_sec^(UINT_MAX);
-	//dev_info(dev, "Write cur_sec(%lu) [0x%08X, 0x%08X] to flash\n", cur_sec, *(unsigned int*)buf, *(unsigned int*)&buf[4]);
-	dev_info(dev, "Write cur_sec(%lu) [0x%08X, 0x%08X] to flash\n", cur_sec, buf[0], buf[1]);
+//	dev_info(dev, "Write cur_sec(%lu) [0x%08X, 0x%08X] to flash\n", cur_sec, buf[0], buf[1]);
 
 	if( !mtd_erase(mtd, &ei) && !(mtd_write(mtd, 0, sizeof(buf), (size_t *)&retlen, (unsigned char *)buf))) {
-		dev_info(dev, "Erase/Write %d bytes successfully\n", retlen);
+//		dev_info(dev, "Erase/Write %d bytes successfully\n", retlen);
 		return 0;
 	}
 	else {
@@ -351,8 +351,8 @@
 	unsigned long cur_sec;
 	unsigned int err = 0;
 
-	dev_info(dev,"set time %04d-%02d-%02d %02d:%02d:%02d", tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday,
-					tm->tm_hour, tm->tm_min, tm->tm_sec);
+//	dev_info(dev,"set time %04d-%02d-%02d %02d:%02d:%02d", tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday,
+//					tm->tm_hour, tm->tm_min, tm->tm_sec);
 
 	cur_sec = mktime(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
 
--- arch/arm64/boot/dts/realtek/wd-monarch-1GB.SATA.dts	2021-07-07 21:45:25.000000000 +0000
+++ arch/arm64/boot/dts/realtek/wd-monarch-1GB.SATA.dts	2021-07-07 13:19:49.113800556 +0000
@@ -89,6 +89,16 @@
         };
     };
 
+    // https://www.kernel.org/doc/Documentation/devicetree/bindings/leds/leds-pwm.txt
+    pwmleds {
+        compatible = "pwm-leds";
+        pwm3{
+          label = "led";
+          pwms = <&pwm 3 37878>;
+          max-brightness = <255>;
+       };
+    };
+
     rtk-rstctrl@0x98007000 {
         compatible = "Realtek,rtk-rstctrl";
         reg = <0x98007600 0x100>;
--- arch/arm64/boot/dts/realtek/rtd-129x-ion-1GB.dtsi	2021-07-07 21:45:25.000000000 +0000
+++ arch/arm64/boot/dts/realtek/rtd-129x-ion-1GB.dtsi	2021-10-24 12:35:56.901198634 +0000
@@ -1,16 +1,16 @@
 #include <dt-bindings/soc/rtk,memory.h>
 
-#define MEDIA_REQ_SIZE_0        (0x0b800000) // 184M
+#define MEDIA_REQ_SIZE_0        (0x00000400) // 1M
 #define ION_MEDIA_HEAP_PHYS_0   (MEM_SLOT(0, PHYS, MEDIA_REQ_SIZE_0))
 #define ION_MEDIA_HEAP_SIZE_0   (MEM_SLOT(0, SIZE, MEDIA_REQ_SIZE_0))
 #define ION_MEDIA_HEAP_FLAG_0   (MEM_SLOT(0, FLAG, MEDIA_REQ_SIZE_0))
 
-#define AUDIO_REQ_SIZE_0        (0x00c00000) // 12M
+#define AUDIO_REQ_SIZE_0        (0x00000400) // 1M
 #define ION_AUDIO_HEAP_PHYS_0   (MEM_SLOT(1, PHYS, AUDIO_REQ_SIZE_0))
 #define ION_AUDIO_HEAP_SIZE_0   (MEM_SLOT(1, SIZE, AUDIO_REQ_SIZE_0))
 #define ION_AUDIO_HEAP_FLAG_0   (MEM_SLOT(1, FLAG, AUDIO_REQ_SIZE_0))
 
-#define MEDIA_REQ_SIZE_1        (0x03c00000) // 60M
+#define MEDIA_REQ_SIZE_1        (0x00000400) // 1M
 #define ION_MEDIA_HEAP_PHYS_1   (MEM_SLOT(2, PHYS, MEDIA_REQ_SIZE_1))
 #define ION_MEDIA_HEAP_SIZE_1   (MEM_SLOT(2, SIZE, MEDIA_REQ_SIZE_1))
 #define ION_MEDIA_HEAP_FLAG_1   (MEM_SLOT(2, FLAG, MEDIA_REQ_SIZE_1))
--- drivers/watchdog/rtd1295_wdt.c.orig	2021-11-15 19:02:22.616220897 +0000
+++ drivers/watchdog/rtd1295_wdt.c	2021-11-15 19:04:12.976266968 +0000
@@ -357,3 +357,7 @@
 };
 
 module_platform_driver(rtd1295_watchdog_driver);
+
+MODULE_DESCRIPTION("Realtek RTD-1295 hardware watchdog driver");
+MODULE_AUTHOR("Western Digital");
+MODULE_LICENSE("GPL v2");